[myhdl-list] Starting with MyHDL and trying to do my Cordic Module
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From: André P. <and...@gm...> - 2014-07-03 21:58:51
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Hello everyone, I am trying to start with MyHDL! I have FPGA design experience with VHDL in the old school style. I am trying to implement my Cordic module which works in VHDL (Converts from REAL/IMAG to MAG/ANG) However I am getting this error when I try to convert to VHDL: KeyError: 'real_reg' and a long traceback list error The module is not 100% functional yet, It's the first time I am doing and I confess I am struggling with this different paradigm, It's not VHDL and it's not Matlab, it's somewhere in the middle hah. This is my testbench: http://pastebin.com/zqRQxbGL This is my Cordic module at the moment: http://pastebin.com/tRU85uwe The testbench seems to be OK but I can't generate the VHDL, Thank you very much; -- Atenciosamente/Regards André Castelan Prado |