Re: [myhdl-list] cosimulated verilog as an instance?

[Henry G. <he...@ca...>]

On 26/05/14 16:36, Christopher Felton wrote:
>> >
>> >Yeah, I'm aware of this problem and I haven't quite worked out the
>> >solution. I'm hoping there is an adequate simulation model for the
>> >blocks I need that aren't encrypted (simple things like the DSP48) until
>> >I can justify an expensive license for modelsim or something.
>> >
>>> >>ps. If it is specifically a question of Xilinx IP, then you could
>>> >>implement co-simulation for isim (which Xilinx provides for free). I
>>> >>don't know how much work that would be, it depends on whether isim
>>> >>supports VPI.
>> >
>> >As far as I can tell, VPI is not supported. I shall report back if I
>> >find out something interesting!
>> >
> I concur, I don't believe isim supports any foreign language
> interfaces, no PLI/VPI/DPI, etc.

Something interesting actually occurred to me today - considering a 
device like a Xilinx Zynq with an on-die ARM Cortex A9, one could 
actually run a Python test bench on the device itself. This is something 
that lends itself to Python as it's already running on such a platform.

It would be lovely to run the same Python test bench on the device as is 
being used for development - at least on the system level.

Cheers,

Henry