Re: [myhdl-list] cosimulated verilog as an instance?

[Henry G. <he...@ca...>]

On 24/05/14 23:38, Per Karlsson wrote:
> Usually simulation models for commercial IP:s come as encrypted RTL, 
> and so far as I'm aware you cannot simulate encrypted RTL in any 
> currently available tool based on open source. You'll simply have to 
> fork up the cash for a commercial, closed source, simulation tool.
> But if you do, there is nothing preventing you from instanciating the 
> IP in a MyHDL module using user defined code and then driving it with 
> a MyHDL testbench using co-simulation.
>
> The greater question is of course whether an open source tool could in 
> theory simulate encrypted RTL, but I leave that for people better 
> versed in cryptography than myself.
> It is also not a question with which MyHDL needs to bother itself, 
> because it has nothing to do with the language. It concerns only the 
> simulator.
>

Yeah, I'm aware of this problem and I haven't quite worked out the 
solution. I'm hoping there is an adequate simulation model for the 
blocks I need that aren't encrypted (simple things like the DSP48) until 
I can justify an expensive license for modelsim or something.

> ps. If it is specifically a question of Xilinx IP, then you could 
> implement co-simulation for isim (which Xilinx provides for free). I 
> don't know how much work that would be, it depends on whether isim 
> supports VPI.

As far as I can tell, VPI is not supported. I shall report back if I 
find out something interesting!

Cheers,

Henry