Re: [myhdl-list] cosimulated verilog as an instance?

[Christopher F. <chr...@gm...>]

On 5/24/14 5:32 AM, Henry Gomersall wrote:
> Consider the use case in which one wishes to use a piece of
> off-the-shelf IP, which comes with a suitable simulation library (let's
> say some Xilinx IP with a unisim library).
>
> I have a notion that I want to be able to generate an instance of the
> simulated model for incorporation into a MyHDL design, so when run, it
> executes in the cosimulation environment. This would remove the
> requirement to reimplement the logic of an IP block in MyHDL.
>
> In conjunction with user defined code, this would allow a neat way to
> incorporate commercial blocks into the design.
>
> Is all this sensible? Is there a better way to do it?


I don't think this would be a small addition/change and I am
not certain if it is possible, it would take some experimentation
etc.

The solution that I am aware of is to use a module to emulate
the IP but this can take some work to get the timing of the
interfaces and the behavior correct.   When creating the module
to emulate the IP you can use the /v*_code/ or /v*_instance/
to generate the V* to instantiate the IP.

Regards,
Chris