[myhdl-list] cosimulated verilog as an instance?
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jandecaluwe
From: Henry G. <he...@ca...> - 2014-05-24 10:32:33
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Consider the use case in which one wishes to use a piece of off-the-shelf IP, which comes with a suitable simulation library (let's say some Xilinx IP with a unisim library). I have a notion that I want to be able to generate an instance of the simulated model for incorporation into a MyHDL design, so when run, it executes in the cosimulation environment. This would remove the requirement to reimplement the logic of an IP block in MyHDL. In conjunction with user defined code, this would allow a neat way to incorporate commercial blocks into the design. Is all this sensible? Is there a better way to do it? Cheers, Henry |