Re: [myhdl-list] missing cast in toVHDL conversion

[Christopher F. <chr...@gm...>]

On 5/19/14 5:06 PM, Christopher Felton wrote:
> On 5/19/14 3:47 PM, Josy Boelen wrote:
>> Josy Boelen <josy <at> c-cam.be> writes:
>>
>>>
>>> When setting toVHDL.numeric_ports = False
>>> the following construct:
>>>       simx.next = DVectors - DObj
>>>
>>> gets converted into:
>>>       ed_ed_edc_0_simx <= signed(resize(DVectors(18-1 downto 0), 19) -
>> unsigned
>>> (DObj));
>>>
>>> where it should be:
>>> either
>>>        ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors)(18-1 downto 0),
>> 19)
>>> - unsigned(DObj));
>>> (or  ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors(18-1 downto 0)),
>> 19)
>>> - unsigned(DObj));)
>>>
>>> Both DObj and DVectors are ports
>>> For now I can live with the workaround of not setting
>> toVHDL.numeric_ports to
>>> False, but at some point in the future I will have to expose
>>> std_logic_vectors in stead of unsigned ports (as this is what Altera's
>> Qsys
>>> allows for VHDL-based components)
>>>
>>> Best regards,
>>>
>>> Josy
>>>
>>>
>> ----------------------------------------------------------------------------
>> No takers?
>> Do I have to move it to the bug report list?
>>
>> Regards,
>>
>> Josy
>>
>
> That might be the best bet, I haven't read the details
> yet and some of these features I have not used (I will
> not be of much use in the near future :)
>
> You can log it as an issue here:
> https://bitbucket.org/jandecaluwe/myhdl/issues?status=new&status=open
>

Note, if you add it to the issue tracker it probably is
a feature request.  As noted by another user .numeric_port
is not an advertised feature.  I don't know if it is complete
or not.  You might want to add an issue as "enhancement" and
for the completion of the feature.

Regards,
Chris