[myhdl-list] missing cast in toVHDL conversion

[Josy B. <jo...@c-...>]

When setting toVHDL.numeric_ports = False
the following construct:
    simx.next = DVectors - DObj

gets converted into:
    ed_ed_edc_0_simx <= signed(resize(DVectors(18-1 downto 0), 19) - unsigned
(DObj));

where it should be:
either
     ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors)(18-1 downto 0), 19) 
- unsigned(DObj));
(or  ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors(18-1 downto 0)), 19) 
- unsigned(DObj));)

Both DObj and DVectors are ports
For now I can live with the workaround of not setting toVHDL.numeric_ports to 
False, but at some point in the future I will have to expose 
std_logic_vectors in stead of unsigned ports (as this is what Altera's Qsys 
allows for VHDL-based components)

Best regards,

Josy