Re: [myhdl-list] to_VHDL: last 'elif .. :' translates to 'when others =>'

[Josy B. <jo...@c-...>]

Josy Boelen <josy <at> c-cam.be> writes:

> 
> When converting a state machine MyHDL translates the last 'elif ... :' 
>
>...
>
> As a side effect it 'repaired' a case where toVHDL 
> lumped together several states into a single 'when others =>' block and 
> generated 'if then else' constructs to elaborate those lumped-in states.
> 
> Regards,
> 
> Josy

I must edit the last sentence: apparently the 'tangled state machine case' 
is in another module ... I'll post a follow up thread on this later

Regards,

Josy