[myhdl-list] to_VHDL: last 'elif .. :' translates to 'when others =>'

[Josy B. <jo...@c-...>]

When converting a state machine MyHDL translates the last 'elif ... :' into 
a 'when others =>'statement.
I felt this is rather impure so I looked in the _toVHDL.py source and 
changed the following around line 1146:
#07-05-2014 jb: do not use default clause for last test
#         for i, (test, suite) in enumerate(node.tests):
        for _, (test, suite) in enumerate(node.tests):
            self.writeline()
            item = test.case[1]
            if isinstance(item, EnumItemType):
                itemRepr = item._toVHDL()
            else:
                itemRepr = self.BitRepr(item, obj)
            comment = ""
#             # potentially use default clause for last test
#             if (i == len(node.tests)-1) and not node.else_:
#                 self.write("when others")
#                 comment = " -- %s" % itemRepr
#             else:
#                 self.write("when ")
#                 self.write(itemRepr)
            self.write("when ")
            self.write(itemRepr)
#07-05-2014 end
That did the trick. As a side effect it 'repaired' a case where toVHDL 
lumped together several states into a single 'when others =>' block and 
generated 'if then else' constructs to elaborate those lumped-in states.

Regards,

Josy