[myhdl-list] to_VHDL adds a signed(resize()( , ) when comparing intbv to a 'constant value'

[Josy B. <jo...@c-...>]

The following code:
def module(...  , D, ... ,  Q, ...):
     L_WIDTH_D = len(D)
     L_WIDTH_Q = len(Q)
     L_N = L_WIDTH_D / L_WIDTH_Q

     counter = Signal(intbv(0 , min = 0, max = L_N))
...
          if counter == L_N - 1:

gets translated into VHDL as :
signal counter: unsigned(1 downto 0);
...
          if (signed(resize(counter, 3)) = (L_N - 1)) then

In VHDL I would have simply written the test as:
          if ( counter = (L_N - 1) ) then
and I don't see why MyHDL should do different. Perhaps, as Python doesn't 
know 'constants' it interprets 'L_N - 1' as a possibly signed value?

Regards,

Josy