[myhdl-list] User-defined code in submodules

[Guy E. <gu...@no...>]

Hello,

is there anything wrong with the following code? What I'm seeing is that 
the generated VHDL code does not include the specified user-defined code.

    from myhdl import *

    def top(nextCount, count, n):

         def inc_comb(nextCount, count, n):
             @always(count)
             def logic():
                 # do nothing here
                 pass

             nextCount.driven = "wire"
             return logic

         inc_comb.vhdl_code =\
         """
         $nextCount <= ($count + 1) mod $n;
         """

         inst_inc_comb = inc_comb(nextCount, count, n)

         return instances()

    if __name__ == '__main__':
         nextCount = Signal(intbv(0)[8:])
         count = Signal(intbv(0)[8:])
         n = 8
         inst_top = toVHDL(top, nextCount, count, n

Regards,
Guy.