Re: [myhdl-list] intbv bit slicing in component instantiation

[Christopher F. <chr...@gm...>]

On 4/22/14 5:02 AM, Josy Boelen wrote:
> While building a list of generated components:
>     elements = [None for _ in range(RATIO_BA)]
>     for i in range(RATIO_BA):
>        elements[i] = ram3port( NUM_ENTRIES / RATIO_BA, WIDTH_D,
>                             clkA, laddressa , dataA, wren_Z[i],
>                             lqa[(i+1) * WIDTH_D : i * WIDTH_D],
>                             clkB, addressB, lqb[(i+1) * WIDTH_D : i * WIDTH_D],
>                             0 , 0 )
> 1. The simulator showed that the wren_Z[i] had no effect. I experimented with
> different techniques to generate the wren_Z intbv signal, but no result...
> Until I checked some examples on the MyHDL web-site, and there I found the
> use of wren_Z(i) which was well accepted. This differs from the MyHDL
> reference:
>     Operation	Result  	 Notes
>     bv[i]	item i of bv	(1)
>

An /intbv/ bits need to stay together, assuming:

     wren_Z = intbv(0)[RATIO_B:]

If you want to separate the bits you need to create
/SliceSignals/ [1][2] as you did, with the "()" instead
of "[]".  The reason is, each bit needs a /Signal/ to
each module.

Since you do not use the collection of bits (wren_Z) as
a whole (e.g. to represent a bounded integer) you can
define it as:

     wren_Z - [Signal(bool(0)) for _ in range(RATIO_BA)]

and use a list of signals as the bit-vector instead of an
/intbv/ then you do not need to break out the /SliceSignals/
and it can be driven from multiple sources.

>
> 2. The to_VHDL convertor flagged that lqa and lqb were not driven. Does that
> mean that we can not connect a slice of an intbv to receive the output of a
> component? I worked around that by changing the single Signal(intbv(0)
> [WIDTH_D*RATIO_BA:]) into  [Signal(intbv(0)[WIDTH_D:]) for _ in range
> (RATIO_BA)] which I could then connect as lqa[i] and lqb[i]. I then manually
> assembled the bigger output intbv from the parts.
>

In general you can not drive slice signals from multiple
generators - if that were the case you should see an error
in conversion (see [2] for more information and background).
These signals must not be driven anywhere to receive the not
driven message.

Regards,
Chris


[1] 
http://docs.myhdl.org/en/latest/manual/structure.html#converting-between-lists-of-signals-and-bit-vectors
[2] http://dev.myhdl.org/meps/mep-105.html