[myhdl-list] intbv bit slicing in component instantiation

[Josy B. <jo...@c-...>]

While building a list of generated components:
   elements = [None for _ in range(RATIO_BA)]
   for i in range(RATIO_BA):
      elements[i] = ram3port( NUM_ENTRIES / RATIO_BA, WIDTH_D,
                           clkA, laddressa , dataA, wren_Z[i], 
                           lqa[(i+1) * WIDTH_D : i * WIDTH_D],
                           clkB, addressB, lqb[(i+1) * WIDTH_D : i * WIDTH_D],
                           0 , 0 ) 
1. The simulator showed that the wren_Z[i] had no effect. I experimented with 
different techniques to generate the wren_Z intbv signal, but no result...
Until I checked some examples on the MyHDL web-site, and there I found the 
use of wren_Z(i) which was well accepted. This differs from the MyHDL 
reference:
   Operation	Result  	 Notes
   bv[i]	item i of bv	(1)


2. The to_VHDL convertor flagged that lqa and lqb were not driven. Does that 
mean that we can not connect a slice of an intbv to receive the output of a 
component? I worked around that by changing the single Signal(intbv(0)
[WIDTH_D*RATIO_BA:]) into  [Signal(intbv(0)[WIDTH_D:]) for _ in range
(RATIO_BA)] which I could then connect as lqa[i] and lqb[i]. I then manually 
assembled the bigger output intbv from the parts.