[myhdl-list] Verification of signed intbv

[Euripedes R. F. <roc...@gm...>]

Hi,
I'm using myhdl as a verification language with sucess so far. I'm using
python unittes to structurc my tests and now I'm facing a problem with the
assertion when I have negative numbers.

My tests are structured with a stimulus and a check module, the relevant
code:

 stimulus(port list):
       for i in test_signal_list :
               input.next = intbv(i, min = -16,max = 16)
               yield posdge(clk)

check(port list):
       assertEqual(test_signal, outport)

I hope that the code above make my approach clear. The fact is that when I
have a negative input the assert fail(-8 in -> 8 out) the module under test
don't make any modification in this ports the signal just goes out
untouched, the module job is to place a set of outputs '1' to route the
signal, the port goes through the module just to have a standart interface.
I can't figure what I'm doing wrong. Someone can help me?

regards

Euripedes