Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Christopher F. <chr...@gm...>]

On 3/24/14 3:51 AM, Jan Decaluwe wrote:
> On 03/23/2014 05:45 PM, Christopher Felton wrote:
>> On 3/23/14 7:31 AM, Guy Eschemann wrote:
>>> Hello,
>>>
>>> I was wondering whether one of you MyHDL wizards would like to answer a
>>> question I posted on Stackoverflow:
>>> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>>>
>>
>> This is a little odd - I don't believe you should
>> get an /inout/ if you use /o_count/ directly.
>
> Yes you should, as per VHDL semantics. You can't read
> an output port in VHDL, but you can in Verilog.
>
> I answered on stack overflow.
>

Ah, that is right, thanks for the clarification
so many tidbits easily forgotten.

Regards,
Chris