Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Guy E. <gu...@no...>]

It looks like there are two aspects in this question, which can be 
addressed separately:

1. Directly incrementing "o_count" yields an inout port in the generated 
VHDL, but only when I convert this module stand-alone (which I did only 
for test purposes) -> that's OK for me.

2. Connecting an internal signal to an output port requires three lines 
of code in MyHDL:

    @always_comb
    def outputs():
         o_count.next = s_count

That's one of the rare cases where MyHDL seems to be more verbose than 
VHDL. In VHDL, this would be a one-liner:

    o_count <= std_logic_vector(s_count);

Regards,
Guy.

Am 24.03.2014 09:51, schrieb Jan Decaluwe:
> On 03/23/2014 05:45 PM, Christopher Felton wrote:
>> On 3/23/14 7:31 AM, Guy Eschemann wrote:
>>> Hello,
>>>
>>> I was wondering whether one of you MyHDL wizards would like to answer a
>>> question I posted on Stackoverflow:
>>> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>>>
>> This is a little odd - I don't believe you should
>> get an /inout/ if you use /o_count/ directly.
> Yes you should, as per VHDL semantics. You can't read
> an output port in VHDL, but you can in Verilog.
>
> I answered on stack overflow.
>
>

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