Re: [myhdl-list] Connect internal signal to output port in MyHDL module
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From: Jan D. <ja...@ja...> - 2014-03-24 08:52:16
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On 03/23/2014 05:45 PM, Christopher Felton wrote: > On 3/23/14 7:31 AM, Guy Eschemann wrote: >> Hello, >> >> I was wondering whether one of you MyHDL wizards would like to answer a >> question I posted on Stackoverflow: >> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module >> > > This is a little odd - I don't believe you should > get an /inout/ if you use /o_count/ directly. Yes you should, as per VHDL semantics. You can't read an output port in VHDL, but you can in Verilog. I answered on stack overflow. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |