Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Christopher F. <chr...@gm...>]

> full example here:
> https://gist.github.com/cfelton/9725726
> or try it out here http://www.edaplayground.com/x/3Aj
> Note the example doesn't address the OT questions, it
> shows the port mismatch between Verilog and VHDL.

Above it should be "OP's question" not "OT".

chris