Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Christopher F. <chr...@gm...>]

On 3/23/14 7:31 AM, Guy Eschemann wrote:
> Hello,
>
> I was wondering whether one of you MyHDL wizards would like to answer a
> question I posted on Stackoverflow:
> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>

This is a little odd - I don't believe you should
get an /inout/ if you use /o_count/ directly.

If it is the expected (I don't think it should be)
then there is a mismatch between the generated Verilog
and VHDL.

Here is my slightly modified version, using the
0.8 features.


     def m_counter(i_clk, i_reset, o_count):
         @always_seq(i_clk.posedge, reset=i_reset)
         def rtl_count():
             o_count.next = o_count + 1

     return rtl_count

     i_clk = Signal(bool(0))
     i_reset = ResetSignal(0, active=1, async=False)
     o_count = Signal(modbv(0, min=0, max=256))
     toVHDL(m_counter, i_clk, i_reset, o_count)
     toVerilog(m_counter, i_clk, i_reset, o_count)

full example here:
https://gist.github.com/cfelton/9725726
or try it out here http://www.edaplayground.com/x/3Aj
Note the example doesn't address the OT questions, it
shows the port mismatch between Verilog and VHDL.

The following is the generated port definitions for
VHDL and Verilog.  The /inout/ direction was only
generated in the VHDL?  This was generated with 0.8.1.

~~~[VHDL]~~~
     entity m_counter is
         port (
             i_clk: in std_logic;
             i_reset: in std_logic;
             o_count: inout unsigned(7 downto 0)
         );
     end entity m_counter;

~~~[Verilog]~~~
     module m_counter (
         i_clk,
         i_reset,
         o_count
     );
     input i_clk;
     input i_reset;
     output [7:0] o_count;
     reg [7:0] o_count;


If no one disagrees this is undesired, I can create
a bug ticket on bitbucket.

As for you question, I don't think there is an
alternative in the current release.

Regards,
Chris