Re: [myhdl-list] simulation coding vs conversion coding

[Christopher F. <chr...@gm...>]

On 3/12/14 4:25 PM, Keerthan jai.c wrote:
> Chris, can you confirm whether this works for you?
> This does not work for me with 0.8 or 0.9dev upstream.
>
> The code I tried is here:
> https://gist.github.com/9516513
>
> I ran into this problem a few months ago, and implemented a fix for
> verilog in this commit:
> https://bitbucket.org/jck2/myhdl/commits/68d86530af4e8a7cd9fb9ca0102a97ebbb93bbb9?at=sf-hotfixes
> I have not sent a PR yet since I didn't investigate this properly.
>

Yes, I observe the error with 0.8.1 and 0.9dev.

I don't recall if this is a known limitation or error?

This is a valid work around though:

     def ab(in1,out1):
         one=[Signal(intbv(0)[2:]) for k in range(2)]
         item = Signal(in1.val)

         @always_comb
         def comb1():
             item = one[0]
             item.next[0] = in1

         always_comb
         def comb2():
             one[0].next = item

         @always_comb
         def comb3():
             out1.next=one[0][0]

         return instances()

Regards,
Chris