Re: [myhdl-list] simulation coding vs conversion coding

[Keerthan jai.c <jck...@gm...>]

Chris, can you confirm whether this works for you?
This does not work for me with 0.8 or 0.9dev upstream.

The code I tried is here:
https://gist.github.com/9516513

I ran into this problem a few months ago, and implemented a fix for verilog
in this commit:
https://bitbucket.org/jck2/myhdl/commits/68d86530af4e8a7cd9fb9ca0102a97ebbb93bbb9?at=sf-hotfixes
I have not sent a PR yet since I didn't investigate this properly.

Lars, you could try making this change to _toVHDL.py and see if it works.



On Tue, Mar 11, 2014 at 7:13 AM, Christopher Felton
<chr...@gm...>wrote:

> On 3/11/14 1:59 AM, Marcel Hellwig wrote:
> > Hi Lars,
> >> one=[Signal(intbv(0)[2:]) for k in range(2)]
> > do this instead:
> >
> >> one, two = [Signal(intbv(0)[2:]) for k in range(2)]
> >
> > it should avoid your problem.
> >
>
> I believe Lars is trying to use a list of signals, the
> above won't work.  You can use list of signals to model
> memory or other logical structures.
>
>
> http://www.myhdl.org/doc/current/manual/conversion_examples.html?highlight=list%20signals#ram-inference
>
> What was posted is the correct approach to bit slice
> into the individual intbv in the list.
>
>      one[n].next[b] = in
>          |       |
>          |       +- intbv bit index
>          +--------- list index
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> Learn Graph Databases - Download FREE O'Reilly Book
> "Graph Databases" is the definitive new guide to graph databases and their
> applications. Written by three acclaimed leaders in the field,
> this first edition is now available. Download your free book today!
> http://p.sf.net/sfu/13534_NeoTech
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck