Re: [myhdl-list] @always_comb - Conversion Error

[Jan D. <ja...@ja...>]

Did you simulate this?

I don't think so. But you should:

http://www.myhdl.org/doc/current/manual/conversion.html#simulate-first

Any operation on a Signal, including slicing, operates on the
underlying value. In particular, slicing a Signal of an intbv
returns an intbv, not a Signal.

In other words, the "signal" aspect of your inputs is gone
and I don't see how this can work. And if it doesn't work,
conclusions about convertibility are meaningless.

On 02/11/2014 02:29 AM, Carlos Silva wrote:
> Hi,
>
> I´ve had been using MyHDL to generate dynamic Verilog code directly from a
> python program. Leaving apart some natural difficulties due to my need of
> dynamic number of inputs and input widths, I´m facing a problem with an
> instance that I thought will be simple to implement, but returned me an
> unexpected error.
>
> Im trying to implement a simple 8x3 multiplexer and I receive the following
> error:
>
> Traceback (most recent call last):
>    File "C:\ECLIPSE\Scales_verilog\DYN\average_hw.py", line 624, in <module>
>      N_TRUNC, N_CALIB)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_toVerilog.py", line
> 135, in __call__
>      genlist = _analyzeGens(arglist, h.absnames)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", line
> 168, in _analyzeGens
>      raise ConversionError(_error.UnsupportedType, n, info)
> myhdl.ConversionError: File C:\ECLIPSE\Scales_verilog\DYN\HDW.py, line 182:
> Object type is not supported in this context: in4
>
> The related parts of my code are:
>
>      n0 = Signal(intbv(15))[12:0]
>      n1 = Signal(intbv(31))[12:0]
>      n2 = Signal(intbv(63))[12:0]
>      n3 = Signal(intbv(127))[12:0]
>      n4 = Signal(intbv(255))[12:0]
>      n5 = Signal(intbv(511))[12:0]
>      n6 = Signal(intbv(1023))[12:0]
>      n7 = Signal(intbv(2047))[12:0]
>      db6 = Signal(intbv(0)[12:0])
>      n = Signal(intbv(0)[3:0])
>      U_25 = Mux_8(n0, n1, n2, n3, n4, n5, n6, n7, db6, n)
>
> # Multiplexer (8 inputs, 3 bits selector)
> def Mux_8(in0, in1, in2, in3, in4, in5, in6, in7, out, sel):
>      @always_comb
>      def logic():
>          if sel == 0x0:
>              out.next = in0
>          elif sel == 0x1:
>              out.next = in1
>          elif sel == 0x2:
>              out.next = in2
>          elif sel == 0x3:
>              out.next = in3
>          elif sel == 0x4:
>              out.next = in4
>          elif sel == 0x5:
>              out.next = in5
>          elif sel == 0x6:
>              out.next = in6
>          else:
>              out.next = in7
>      return instances()
>
>
> I have edited manually the code of "_extractHierarchy" with some print
> statements to obtain the types for each input, and it stops at in4, with the
> following sequence of prints:
>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._intbv.intbv'>
>
>
> The original type of all the inputs is <class 'myhdl._intbv.intbv'>.
>
> Using python 2.7 under Eclipse with Pydev and MyHDL 0.8.
>
>
> Any sugestions?
>
>
>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
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