Re: [myhdl-list] MEP 107 need for portmap

[Keerthan jai.c <jck...@gm...>]

I'm not sure which approach is more pythonic in this scenario. However,
currently the only interface to the conversion functions are through toV*
attributes. I think it is more 'consistent' to use toVerilog.portmap,
unless we make the other parameters(such as toVerilog.name) exposed through
top level function attributes too.


On Fri, Feb 14, 2014 at 8:50 AM, Christopher Felton
<chr...@gm...>wrote:

> Previously, we had a short discussion that the MEP107
> interface conversion for top-levels (e.g modules being
> converted) introduced a need for a generated /portmap/ [1].
>
> The main uses case, given a module:
>
>      def m_some_mod(ifc1, ifc2):
>          # ...
>
> If I am verifying the above module via co-simulation,
> without a /portmap/ I would need to manually write a
> wrapper or manually breakout all the interface /Signals/
> when building the /Cosimulation/, example:
>
>      Cosimualation(simcmd, ifc1_di=ifc1.di, ifc1_do=ifc1.do ...
>
> In this case it defeats the purpose of the interfaces.
> To address this complication Keerthan proposed a /portmap/
> be generated in the conversion functions, the above would
> then become:
>
>      Cosimulation(simcmd, **portmap)
>
> Ahhh, much better :)
>
> The /toV*/ functions already return a list generators in
> the module.  The /portmap/ can't be returned from the
> /toV*/ functions without breaking backwards compatibility.
>
> The current proposal is to attach a function attribute to the
> /toV*/ functions, e.g:
>
>      toVerilog.portmap
>
> The /toV*.portmap/ would be the dictionary of the converted
> portmap (interface expanded names).
>
> I would like to propose and discuss attaching the /portmap/
> attribute to the function being converted and not the
> conversion functions.  To me this is a more natural (I don't
> know if this is generally pythonic (accepted) to have other
> functions modify and/or add attributes to other functions).
>
> In addition, I would propose that generated portmap saved
> in the /vportmap/ attribute and the /portmap/ attribute
> to be used as a user defined default port definition.
>
> Keerthan has done an amazing job implementing MEP-107, many
> thanks!  He has also created a pull-request for the
> /toVerilog.portmap/, I wanted to have a short discussion
> and make sure this is the most flexible path moving forward.
> Once we finalize the portmap I can update the MEP.
>
> Regards,
> Chris
>
> [1] http://thread.gmane.org/gmane.comp.python.myhdl/3223/focus=3318
>
>
>
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-- 
have a nice day
-jck