Re: [myhdl-list] Dynamic ports

[Carlos S. <car...@sa...>]

Yes, I confirm that the first method didn´t solve the problem (the design 
was built without ports, this time, as the ports were not recognized 
automatically by Verilog Converter).

I will try this second approach and give you feedback.

I also found another article posted by you:
http://www.fpgarelated.com/showarticle/544.php
That presents a new feature available in future MyHDL 0.9 version that seems 
to be a good solution to my problem. But I can´t wait for the new version of 
MyHDL.