[myhdl-list] Dynamic ports

[Carlos S. <car...@sa...>]

Hi,

As I mentioned in a previous post, I´m using MyHDL to generate Verilog code 
directly from an ADC simulation program written in Python.

ADC´s can be generated with different number of stages and different 
resolutions per stage, so, my actual approach is based on the maximum number 
of ports that can be used, and if they aren´t used, they stay disconnected.

But this is not the perfect solution. Ports that are not used appear in final 
design, disconnected, but I need them to be discarded during conversion, to 
build a cleaner final design.

I can generate N different files to generate N different configurations, but 
it is certainly an ugly and heavy solution.

Is it possible to discard disconnected ports during conversion to Verilog?