Re: [myhdl-list] Avoid Latches

[Christopher F. <chr...@gm...>]

On 1/16/2014 11:15 AM, Guy Eschemann wrote:
>
> I like how BSV (Bluespec SystemVerilog) uses the "?" expression for
> specifying "don't care":
>
>               if ( (a==0) && (b==0) )
>                  o = 1;
>               else if ( (a==1) && (b==1) )
>                  o = 0;
>               else
>                  o = ?;


The use of '?' in V/SV is the recommended don't
care for /casez/ statements.  The use of 'x' as a
don't care is a hijacking of the of the definition
(IMO).

But in general, I am not convinced a don't care is
needed at the HDL level.  I think there is a difference
between representing a logical function syntactically
in an HDL vs minimizing a logic expression with inputs
and outputs defined as "don't cares".

In other words, we know logic optimization works great
with simple input output tables but not necessarily
with conditional type descriptions.  It might be the
case we can simplify the HDL description if we don't
even consider don't cares.

     o.next = False if a and b else True
     # which is "not (a and b)"

Regards,
Chris