Re: [myhdl-list] Avoid Latches

[Guy E. <gu...@no...>]

I like how BSV (Bluespec SystemVerilog) uses the "?" expression for 
specifying "don't care":

             if ( (a==0) && (b==0) )
                o = 1;
             else if ( (a==1) && (b==1) )
                o = 0;
             else
                o = ?;

Since BSV uses 2-valued logic, the "?" does not mean 'X'. It just allows 
the compiler to pick whatever value it thinks is more convenient.

Cheers,
Guy.


Am 16.01.2014 15:43, schrieb Christopher Felton:
>> On 15.01.2014 17:12, Christopher Felton wrote:
>>> OT: 'x' in Verilog, is it "don't care" or is it
>>> "unknown" or when is it one or the other :)
>> don't care :)
> Designer use as don't care, simulator as unknown.
>
>>> In an @always_comb there can be no undefined paths,
>>> /dout/ and /iodriverr/ need to be defined for each
>>> logical path.
>> That's why I wanted a don't care value ;)
> See section 3 page 10 from:
> http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf
>
>>> If this is a bus, in an FPGA it is reasonable to
>>> drive the bus to zero when not used, that way the
>>> buses can be "OR'd" together.
>> I use tristates for my bus, but okay. I think that's much easier,
>> because I can 'switch' results on and off to the case I need them.
> Typically, you would only use *tristates* for
> off-chip interfaces.  In an FPGA or ASIC an OR'd [1]
> bus or multiplexed bus would be used.
>
>>>        @always_comb
>>>        def read():
>>>            # default values
>>>            dout.next = 0
>>>            iodriverr.next = 0
>>>
>>>            # conditional values
>>>            if ready:
>>>                dout.next = in_data
>>>                if not hit:
>>>                    iodriverr.next = in_data
>>>
>>> This will prevent the latches.
>> This is one option, but iirc the reason for the don't care value is,
>> that the 'compiler' can optimize the output to make it as effective as
>> possible. But I will use the '0-solution' for now, thanks anyway.
>>
> The 'x' can cause more problems that it is worth.
>
> Here is another paper on Verilog's 'x':
> http://www.sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf
>
> Recall, Verilog is not the standard - more often it
> provides examples how not to do things (sometimes
> leverage the good :)
>
> [1] really any logic the provides an "identity" can
>       be used, the simple case are OR and AND
>       A | 0 = A
>       A & 1 = A
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> CenturyLink Cloud: The Leader in Enterprise Cloud Services.
> Learn Why More Businesses Are Choosing CenturyLink Cloud For
> Critical Workloads, Development Environments & Everything In Between.
> Get a Quote or Start a Free Trial Today.
> http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

-- 
Guy Eschemann
noasic e.K.
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no...
Follow me on Twitter: @geschema
Skype: guy.eschemann
http://noasic.com
http://fpga-exchange.com
http://fpga-news.de
USt-IdNr.: DE266749532
HRA 703582, Amtsgericht Freiburg i. Br.