Re: [myhdl-list] Avoid Latches

[Christopher F. <chr...@gm...>]

> On 15.01.2014 17:12, Christopher Felton wrote:
>> OT: 'x' in Verilog, is it "don't care" or is it
>> "unknown" or when is it one or the other :)
> don't care :)

Designer use as don't care, simulator as unknown.

>> In an @always_comb there can be no undefined paths,
>> /dout/ and /iodriverr/ need to be defined for each
>> logical path.
> That's why I wanted a don't care value ;)

See section 3 page 10 from:
http://www.arm.com/files/pdf/Verilog_X_Bugs.pdf

>> If this is a bus, in an FPGA it is reasonable to
>> drive the bus to zero when not used, that way the
>> buses can be "OR'd" together.
> I use tristates for my bus, but okay. I think that's much easier,
> because I can 'switch' results on and off to the case I need them.

Typically, you would only use *tristates* for
off-chip interfaces.  In an FPGA or ASIC an OR'd [1]
bus or multiplexed bus would be used.

>>       @always_comb
>>       def read():
>>           # default values
>>           dout.next = 0
>>           iodriverr.next = 0
>>
>>           # conditional values
>>           if ready:
>>               dout.next = in_data
>>               if not hit:
>>                   iodriverr.next = in_data
>>
>> This will prevent the latches.
> This is one option, but iirc the reason for the don't care value is,
> that the 'compiler' can optimize the output to make it as effective as
> possible. But I will use the '0-solution' for now, thanks anyway.
>

The 'x' can cause more problems that it is worth.

Here is another paper on Verilog's 'x':
http://www.sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf

Recall, Verilog is not the standard - more often it
provides examples how not to do things (sometimes
leverage the good :)

[1] really any logic the provides an "identity" can
     be used, the simple case are OR and AND
     A | 0 = A
     A & 1 = A

Regards,
Chris