Re: [myhdl-list] Avoid Latches

[Marcel H. <1he...@in...>]

On 15.01.2014 17:12, Christopher Felton wrote:
> OT: 'x' in Verilog, is it "don't care" or is it
> "unknown" or when is it one or the other :)
don't care :)
> In an @always_comb there can be no undefined paths,
> /dout/ and /iodriverr/ need to be defined for each
> logical path.
That's why I wanted a don't care value ;)
> If this is a bus, in an FPGA it is reasonable to
> drive the bus to zero when not used, that way the
> buses can be "OR'd" together.
I use tristates for my bus, but okay. I think that's much easier,
because I can 'switch' results on and off to the case I need them.
>      @always_comb
>      def read():
>          # default values
>          dout.next = 0
>          iodriverr.next = 0
>
>          # conditional values
>          if ready:
>              dout.next = in_data
>              if not hit:
>                  iodriverr.next = in_data
>
> This will prevent the latches.
This is one option, but iirc the reason for the don't care value is,
that the 'compiler' can optimize the output to make it as effective as
possible. But I will use the '0-solution' for now, thanks anyway.

Greetings
Marcel