Re: [myhdl-list] Avoid Latches

[Christopher F. <chr...@gm...>]

On 1/15/2014 9:57 AM, Marcel Hellwig wrote:
> Hi everyone,
>
> currently I'm developing code for a FPGA and have the following code:
>
>> @always_comb
>> def read():
>>      if ready:
>>          dout.next = in_data
>>          if not hit:  # tell the cache the right data, so it can store it
>>              iodriverr.next = in_data
>
> the problem is that Quartus II complains about the following:
>
>> Warning (10240): Verilog HDL Always Construct warning at c25Board.v(358): inferring latch(es) for variable "Memory_MMU_mmuOut", which holds its previous value in one or more paths through the always construct
>
> after talking to my prof I figured out, why this happend and how to
> solve it. Just give the output a default value ('bx in verilog), but
> this is not possible in myhdl, because we do not have a "undefined" or
> don't care value, do we?!
> So, what is the best way to solve this?! I don't like to correct this
> manually in the verilog file every time.
>
> Greetings
> Marcel
>

OT: 'x' in Verilog, is it "don't care" or is it
"unknown" or when is it one or the other :)

In an @always_comb there can be no undefined paths,
/dout/ and /iodriverr/ need to be defined for each
logical path.

If this is a bus, in an FPGA it is reasonable to
drive the bus to zero when not used, that way the
buses can be "OR'd" together.

     @always_comb
     def read():
         # default values
         dout.next = 0
         iodriverr.next = 0

         # conditional values
         if ready:
             dout.next = in_data
             if not hit:
                 iodriverr.next = in_data

This will prevent the latches.

Hope that helps,
Chris