[myhdl-list] Avoid Latches

[Marcel H. <1he...@in...>]

Hi everyone,

currently I'm developing code for a FPGA and have the following code:

> @always_comb
> def read():
>     if ready:
>         dout.next = in_data
>         if not hit:  # tell the cache the right data, so it can store it
>             iodriverr.next = in_data

the problem is that Quartus II complains about the following:

> Warning (10240): Verilog HDL Always Construct warning at c25Board.v(358): inferring latch(es) for variable "Memory_MMU_mmuOut", which holds its previous value in one or more paths through the always construct

after talking to my prof I figured out, why this happend and how to
solve it. Just give the output a default value ('bx in verilog), but
this is not possible in myhdl, because we do not have a "undefined" or
don't care value, do we?!
So, what is the best way to solve this?! I don't like to correct this
manually in the verilog file every time.

Greetings
Marcel