Re: [myhdl-list] MEP-107: Conversion of Attribute Signal Containers

[Christopher F. <chr...@gm...>]

On 1/14/2014 2:00 PM, Guy Eschemann wrote:
> Hello,
>
> I'm not sure whether this has been discussed before, but instead of
> using underscores to create the port names (MyObj_*):
>
>       entity ex1 is
>            port (
>                clk: in std_logic;
>                MyObj_x: in unsigned(7 downto 0);
>                MyObj_y: in unsigned(3 downto 0);
>                MyObj_z: out unsigned(8 downto 0)
>            );
>       end entity ex1;
>
> names could also be mangled by putting them between backslashes, e.g.:
>
>       entity ex1 is
>            port (
>                clk: in std_logic;
>                \MyObj#x\: in unsigned(7 downto 0);
>                \MyObj#y\: in unsigned(3 downto 0);
>                \MyObj#z\: out unsigned(8 downto 0)
>            );
>       end entity ex1;
>
> Not sure whether this would be desirable, though.
>
> Cheers,
> Guy.


We need to support both Verilog and VHDL conversion,
the underscores were a natural choice for both languages.

Regards,
Chris