[myhdl-list] VHDL Conversion Issue

[Guy E. <gu...@no...>]

Hello,

I started using myHDL just a few days ago, and so far things are going 
*really* well.

One issue I've just run into is that the following line of Python code:

    elif s_rom_dout[1+7:3] == intbv("11101"):

gets converted to the following (incorrect) VHDL code:

    elsif (signed(resize(s_rom_dout((1 + 7)-1 downto 3), 6)) =
    string'("11101")) then

Am I doing something wrong, or is that a bug in the converter?

Thanks,
Guy.

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Guy Eschemann
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