Re: [myhdl-list] MEP 107 Initial support

[Christopher F. <chr...@gm...>]

On 10/2/2013 2:45 PM, Keerthan jai.c wrote:
> toVerilog returns whatever would be returned if you called the function
> directly, usually a tuple of generators. So, someone could hypothetically
> have been passing the return value of toVerilog to a myhdl.Simulation
> object. Returning the portmap alongside the previous return value would
> break their code.
>
> toVerilog.portmap seems reasonable.
>
>

How about the /portmap/ is tied to the module
(the function being passed) instead of the toV*?

Because of another request I was thinking - it
could be useful to define the "default" port
types in a /portmap/ function attribute.

Couple benefits:

    1. Top-level modules often are specific, there
       is only one mapping that makes sense

    2. removes the need to re-declare the port
       (simulation and conversion)

Example:

     def m_adder(a,b,c):
         @always_comb
         def rtl():
             c.next = a + b
         return rtl

     iot = intbv(0, min=-8, max=8)
     m_adder.portmap = {"a":Signal(iot),
                        "b":Signal(iot),
                        "c":Signal(iot)}

A /vportmap/ (or something similar) function attribute
could be used to contain the expanded names.  The port
definitions would be tied to the top-level function.

.chris