Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 11/30/2013 10:24 AM, Thomas Heller wrote:
> Am 29.11.2013 18:40, schrieb Christopher Felton:
>>
>> What is it
>> ==========
>> myhdl_tools is a eclectic collection of tools that have been
>> used in various projects and examples.  The tools assist in
>> simulation and FPGA build and other random tasks.
>
> Looks interesting, especially since it creates a command line workflow
> for synthesis which I have never used so far.
> However, here are a few issues I encountered while trying the example
> from the overview webpage (Windows7, xilinx ise 14.1):
>

Yes, the Python controlled flow has been huge
for formal and infomral workshops.  People can
focus on the HDL and the results (working HW)
vs. trying to get the FPGA tools installed and
learning yet another IDE/tool.

<snip>
>
> I have to delete the 'xilinx' file that was created, and create
> a 'xilinx' directory before running the code, then it works.
>
> Trying vhdl instead of verilog, by using 'brd.run("vhdl")' gives this:
>
<snip>
>
> Thomas
>

Thanks for the feedback!  I have fixed these
issues and will push a new release, 0.0.2
ASAP.

Regards,
Chris