Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 29.11.2013 18:40, schrieb Christopher Felton:
>
> What is it
> ==========
> myhdl_tools is a eclectic collection of tools that have been
> used in various projects and examples.  The tools assist in
> simulation and FPGA build and other random tasks.

Looks interesting, especially since it creates a command line workflow
for synthesis which I have never used so far.
However, here are a few issues I encountered while trying the example
from the overview webpage (Windows7, xilinx ise 14.1):

> C:\Users\thomas\devel\hdl>py -2.7-32 -O xula.py
> ('HDL PORTS:  ', {'chan': None})
> ('HDL PARAMS: ', {})
> ** ToVerilogWarning: Output port is read internally: chan
>    checking ./xilinx/xula.v
>    moving xula.v --> ./xilinx/
>    checking ./xilinx/tb_xula.v
>    moving tb_xula.v --> ./xilinx/
> Traceback (most recent call last):
>   File "xula.py", line 20, in <module>
>     brd.run()#"vhdl")
>   File "C:\Python27\lib\site-packages\myhdl_tools\_xilinx.py", line 283, in run
>     self.convert(to=use)
>   File "C:\Python27\lib\site-packages\myhdl_tools\_fpga.py", line 156, in convert
>     shutil.move(src,self._path)
>   File "C:\Python27\lib\shutil.py", line 299, in move
>     copy2(src, real_dst)
>   File "C:\Python27\lib\shutil.py", line 128, in copy2
>     copyfile(src, dst)
>   File "C:\Python27\lib\shutil.py", line 83, in copyfile
>     with open(dst, 'wb') as fdst:
> IOError: [Errno 22] invalid mode ('wb') or filename: './xilinx/'
>
> C:\Users\thomas\devel\hdl>

I have to delete the 'xilinx' file that was created, and create
a 'xilinx' directory before running the code, then it works.

Trying vhdl instead of verilog, by using 'brd.run("vhdl")' gives this:

> C:\Users\thomas\devel\hdl>py -2.7-32 -O xula.py
> ('HDL PORTS:  ', {'chan': None})
> ('HDL PARAMS: ', {})
> ** ToVHDLWarning: Output port is read internally: chan
>    checking ./xilinx/xula.vhd
>    moving xula.vhd --> ./xilinx/
>    checking ./xilinx/tb_xula.vhd
>    checking ./xilinx/pck_myhdl_08dev.vhd
> Traceback (most recent call last):
>   File "xula.py", line 20, in <module>
>     brd.run("vhdl")
>   File "C:\Python27\lib\site-packages\myhdl_tools\_xilinx.py", line 284, in run
>     self.create_ucf(filename=self.name+'.ucf')
> AttributeError: 'XilinxFPGA' object has no attribute 'name'
>
> C:\Users\thomas\devel\hdl>

Thomas