[myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

What is it
==========
myhdl_tools is a eclectic collection of tools that have been
used in various projects and examples.  The tools assist in
simulation and FPGA build and other random tasks.

Main Features
=============

    * Clock, Reset, SignalQueue objects to simplify repetitive
      tasks in simulation.  Example, the Clock object simplifies
      clock generation in simulation and separately passing the
      clock frequency as a argument parameter to modules

    * FPGA build tools, automates the execution of the FPGA
      tools for specific development boards.  A MyHDL top-level
      module can be given to the tools and the ports will
      automatgically mapped to the board definition (if the
      port names match the pin names).

    * Board definitions, a collection of board definitions to
      be used with the FPGA build

    * Cosimulation tools


Where to get it
===============
The repository is hosted on bitbucket:
https://bitbucket.org/cfelton/myhdl_tools/

release download:
https://bitbucket.org/cfelton/myhdl_tools/downloads

and is available on PiPy.  The package can be installed
with pip etc.

    >> pip install myhdl_tools

License
=======
LGPL

Documentation
=============
The current documentation is available at the landing page [1]
on bitbucket.  The sphinx documents will be available in one
of the future releases :)

Background
==========
Roughly a year ago I "dumped" a bunch of common tools into a
package.  These tools did not fit with a particular project.
In some cases I wanted a test area for possible future myhdl
additions.  I first used some of the tools in this package in
the MyHDL LED example [2][3] to automate the FPGA toolflow.
I then used it in the examples for DesignWest 2013 [4][5]
(ESC, EELive) to reduce the number of lines of code in the
examples, and again with the PyOhio workshop [6][7], again to
automate the FPGA flow so the attendees could focus on the HDL
design and not the toolflow.  I have also used it in a couple
of projects [8][9].

Although this is a random collection of  tools these tools
significantly simplify an FPGA flow for MyHDL.

Discussion and Development
==========================
Discussions can occur on the MyHDL mailing-list (assuming
no one has an objection), contributions are welcomed
(encouraged), pull requests can be submitted to the bitbucket
repository [1].  Bugs and feature requests can also be logged
on the bitbucket repository.  An straight-forward contribution
is more board definitions.

Regards,
Chris Felton

[1] https://bitbucket.org/cfelton/myhdl_tools/overview
[2] http://www.fpgarelated.com/showarticle/25.php
[3] 
https://bitbucket.org/cfelton/examples/src/tip/stroby/compile_stroby.py?at=default
[4] 
http://myhdl.org/lib/exe/fetch.php/users:cfelton:esc-329slides_felton_24apr2013.pdf
[5] http://myhdl.org/lib/exe/fetch.php/users:cfelton:esc-329paper_felton.pdf
[6] http://www.fpgarelated.com/showarticle/433.php
[7] http://www.fpgarelated.com/showarticle/437.php
[8] https://bitbucket.org/cfelton/examples
[9] https://github.com/cfelton/minnesota
      note on [9] github was the first home but is a mirror of
      the actual development repo on bitbucket.  Only major
      updates are pushed over.  The mn pkg main IP core at this
      point is the fpgalink core [10], bitbukcet version [11]
[10] https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
[11] https://bitbucket.org/cfelton/minnesota