Re: [myhdl-list] MEP - keep hierarchy in conversion

[Christopher F. <chr...@gm...>]

On 10/4/2013 4:14 PM, Jan Decaluwe wrote:
> On 10/03/2013 11:48 PM, Angel Ezquerra wrote:
>
>> This may be one of those "folklore things" that get told from engineer
>> to engineer, without a proper backup. It may even have been true once,
>> but perhaps it is no longer the case?
>
> [About the need for floorplanning FPGAs]
>
> I have now checked this with competent people that I trust
> and that regularly do large layouts.
>
> They tell me that with current state-of-the-art tools,
> floorplanning within the digital HDL flow doesn't make
> much sense, not for ASICs and not for FPGAs.
>
> On the contrary: "flat" layout tools can do intelligent
> placement automatically, and global placement optimization
> (no artificial boundaries) is advantageous, just like for
> synthesis.
>
> The condition however is a clean design methodology, in
> particular solid conservative synchronous design practices.
>
> Therefore, my hypothesis is that people who claim that
> "floorplanning is essential", like Mr. Karlsson and his
> anynomous "expert", really use it as a workaround for a
> messy methodology.
>

Some additional comments on the need for floorplanning
specifically for FPGAs.  Here are three more opinions [1]
that support the *no* floorplanning (usenet comp.arch.fpga)
At least one commenter suggests restricting (preventing
flattening) causes lower QoR.

[1] 
http://www.fpgarelated.com/comp.arch.fpga/thread/109993/granularity-of-components-for-fpga-synthesis.php