Re: [myhdl-list] MEP - keep hierarchy in conversion

[Angel E. <ang...@gm...>]

El 04/10/2013 23:14, "Jan Decaluwe" <ja...@ja...> escribió:
>
> On 10/03/2013 11:48 PM, Angel Ezquerra wrote:
>
> > This may be one of those "folklore things" that get told from engineer
> > to engineer, without a proper backup. It may even have been true once,
> > but perhaps it is no longer the case?
>
> [About the need for floorplanning FPGAs]
>
> I have now checked this with competent people that I trust
> and that regularly do large layouts.
>
> They tell me that with current state-of-the-art tools,
> floorplanning within the digital HDL flow doesn't make
> much sense, not for ASICs and not for FPGAs.
>
> On the contrary: "flat" layout tools can do intelligent
> placement automatically, and global placement optimization
> (no artificial boundaries) is advantageous, just like for
> synthesis.

That makes sense when you put it like that. That being said, do you know if
your colleagues would consider the Xilinx tools (ISE and/or Vivado) "state
of the art" in this regard?

> The condition however is a clean design methodology, in
> particular solid conservative synchronous design practices.

Do you have any blog post or some other material where you describe what
you would consider "solid conservative synchronous design practices"? I'd
be really interested in what you would have to say on that topic.

> Therefore, my hypothesis is that people who claim that
> "floorplanning is essential", like Mr. Karlsson and his
> anynomous "expert", really use it as a workaround for a
> messy methodology.

Or maybe they use tools which are not state of the art? The tools you use
often frame your way of thinking (as many MyHDL users have probably
discovered).

Also, do you think that making it easy to split the generated code a into
multiple files has real benefits other than floorplanning? If you do, which
ones? Off the top of my head I can think of improved interaction with
version control (when that is necessary) and perhaps making it easier to
understand/find synthesis errors...

Cheers,

Angel