Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 11:48 PM, Angel Ezquerra wrote:

> This may be one of those "folklore things" that get told from engineer
> to engineer, without a proper backup. It may even have been true once,
> but perhaps it is no longer the case?

[About the need for floorplanning FPGAs]

I have now checked this with competent people that I trust
and that regularly do large layouts.

They tell me that with current state-of-the-art tools,
floorplanning within the digital HDL flow doesn't make
much sense, not for ASICs and not for FPGAs.

On the contrary: "flat" layout tools can do intelligent
placement automatically, and global placement optimization
(no artificial boundaries) is advantageous, just like for
synthesis.

The condition however is a clean design methodology, in
particular solid conservative synchronous design practices.

Therefore, my hypothesis is that people who claim that
"floorplanning is essential", like Mr. Karlsson and his
anynomous "expert", really use it as a workaround for a
messy methodology.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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