Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 11:48 PM, Angel Ezquerra wrote:
> On Thu, Oct 3, 2013 at 6:20 PM, Jan Decaluwe <ja...@ja...> wrote:

> I know that I've been told this by a couple of times, by different
> Xilinx instructors, when I did some training classes on the Xilinx ISE
> tools a few years ago. Next time we get some Xilinx guys to visit us I
> will ask them if this is still the case.

Be careful with what Xilinx tells you - they may sell workarounds
for their own problems and limitations as "general FPGA recommendations".

For example, there is this guy (Ken Chapman), a Xilinx fellow, who
recommends fine-grained reset control to reduce resets to a
minimum. An important reason mentioned is saving on routing resources
and avoiding congestion.

The implications for the coding style I'm advocating
and trying to promote with MyHDL would be horribe and scary -
process partitioning just for reset control.

The fact that few complain about this must mean that many
designers work at a fairly low-level - the kind of typical
Verilog-inspired coding that I find horrible.

Now, Altera doesn't have such a recommendation afaik. And guess what,
in their newest architecture it seems that Xilinx will increase
global routing resources drastically. To me, this is evidence
that they recognize that something was wrong with their previous one.

Jan

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