Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 11:48 PM, Angel Ezquerra wrote:

[About the need for floorplanning FPGAs]

> This may be one of those "folklore things" that get told from engineer
> to engineer, without a proper backup.

Sometimes it seems that the HDL design world, especially the Verilog side,
is *only* folklore. Like the absurd recommendation that one
"should not mix blocking and nonblocking assignments". (No problem
at all with local blocking assignments.) I suspect 95+% of the Verilog
world still believes this complete bullshit, at a great cost in good coding
pratices.

Verilog as a language is bad enough, but the real problem is that it
attracts a particular kind of hardware engineer, fond of low-level
thinking and unaware of good programming practices. And the larger
the company, the worse it gets, like with Ericsson and ARM for
example, because then mediocrity (of the hardware designers, not
the company) gets coupled with arrogance.

ARM actually claims that one shouldn't use if-then-else clauses in
HDL code. Instead of questioning the hypotheses that lead to this
obviously absurd conclusion, they make it a recommendation and
a requirement for subcontractors.

Such companies are also full of mediocre engineers that think they
are geniuses just because they have fought Verilog long enough to
get something to work. Then they make Verilog the norm of all things,
no matter how absurd, as the best example of the digital Stockholm
syndrome I know of. And of course, they feel too good to enter into
a rational discussion with those who actually know something about
this stuff, as we just saw. Those are the people that I really
hate in this profession.

> It may even have been true once,
> but perhaps it is no longer the case?

Or it may be true for one vendor and not for another.

Or for one family and not for another.

That's why I ask for evidence: an independent study by
a credible source that compares alternative flows based
on experiments.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com