Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

Digging up a few docs for general edification in the realm of FPGA's,
hierarchical design, partitions, and constraints...


This Altera doc doesn't concisely claim it improves map/plan/route results:
 (in fact, it warns of the contrary...)

"Quartus II Incremental Compilation for Hierarchical and Team-Based Design"
http://www.altera.com/literature/hb/qts/qts_qii51015.pdf

But on the 2nd and 3rd pages, it does intro the trade-offs of "Flat
Compilation Flow with No Design Partitions" vs "Incremental Compilation
Flow With Design Partitions", and the rest of the document is interesting
as well.


And similar docs from Xilinx:

"Vivado Design Suite User Guide: Hierarchical Design"
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug905-vivado-hierarchical-design.pdf
page 4: "Users can iterate on a specific section of a design, achieving
timing closure and other specific goals, then reuse those exact results
while turning their attention to other parts of the design."

"Hierarchical Design Methodology Guide" [for ISE, not Vivado]
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/Hierarchical_Design_Methodology_Guide.pdf
page 53:  (block quote)

Design preservation:
• Reduces the number of implementation iterations during timing closure.
Once a portion of the design meets timing, the implementation results
(placement and routing) are used in the next iteration.
• Prevents portions of the design that are complete, and that meet timing,
from being affected by changes in other parts of the design.
• Uses partitions to preserve the previous implementation results for a
module instance.

Using partitions carefully:
• Reduces the number of design iterations.
• Shortens timing closure.
• Eliminates re-verification of unchanged instances.



Also, these appear relevant:
"Advanced Strategies for Improving Performance"
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ise_c_imp_strategies.htm#styler-id1.1.1.12.4.6.3.3.8

"Timing Constraints Recommendations"
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/ise_c_imp_strategies.htm#styler-id1.1.1.12.4.6.3.3.9.1


(general impression:  Tools sometimes need a bit of guidance to get the job
done.)

- David


On Thu, Oct 3, 2013 at 5:48 PM, Angel Ezquerra <ang...@gm...>wrote:

> On Thu, Oct 3, 2013 at 6:20 PM, Jan Decaluwe <ja...@ja...> wrote:
> > On 10/02/2013 12:44 AM, Angel Ezquerra wrote:
> >> I cannot comment on the ASIC side, but on the FPGA side it is a common
> >> recommendation to properly organize your code into entities to improve
> >> the map and/or plan and route results.
> >
> > I have briefly checked the Xilinx docs and I haven't found
> > such a recommendation.
>
> This may be one of those "folklore things" that get told from engineer
> to engineer, without a proper backup. It may even have been true once,
> but perhaps it is no longer the case?
>
> I know that I've been told this by a couple of times, by different
> Xilinx instructors, when I did some training classes on the Xilinx ISE
> tools a few years ago. Next time we get some Xilinx guys to visit us I
> will ask them if this is still the case.
>