Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

A vendor neutral standard would be fantastic.  I notice a number of
references to Synopsys (.sdc) files from both Altera and Xilinx, but I'm
not sure how consistent that is.  [Anyone else have perspective here?]  Not
very vendor neutral, but just yet-another-vendor.  In the case of Xilinx,
their old [ISE] tools offer a variety of (disjoint) formats to specify
timing constraints.  I tend to use .ucf files, since they're simple text
files and easier on my eyes versus the clutter of .xml.  (and very simple
to export from a Python script...)

Personally I'm attracted to the latter approach -- of "generating all the
required files from MyHDL *.py + physical conf *.py depending on the target".
 :)  And for now, leaving the responsibility of dealing with vendor
specific file formats to the end-user --- such as they might generate from
their "physical conf *.py" files.

It would be nice if MyHDL could assist in auto-exporting some of the
assigned net names...  oh... I have another dirty code idea coming on...  I
could have the _convert_filter invoke user callback functions for any
requested signal, memory, or generator.  At that point in the process, all
the names are assigned, so the user can extract whatever names [or other
info?] as necessary to assist with generating constraint files.  Yep,
nasty.  [But then I can assign a "TIG" on that net w/out the nuisance of
manually sync'ing my constraints (.ucf) file when the occasional name
happens...]


On Thu, Oct 3, 2013 at 4:15 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 10/03/2013 09:48 PM, David Holl wrote:
> > <snip>
> > Since this HDL is already in Python, and Python is pretty darn
> > flexible...  Could Python fill that higher role, and perhaps be
> > capable of doing such end-to-end design control?  (ie, in a
> > collection of .py files, some files are just for describing the logic
> > design, while others manage the resource assignment but assisted with
> > a few [as needed] hierarchical names from the logic design?)
>
> A reasonable suggestion. However, if there is already
> a standard, even de facto (I don't know) then reusing it
> might be considered. (I seemed to understand that Xilinx
> uses an xml input format). Alternatively, generating
> all the required files from MyHDL *.py + physical conf *.py
> depending on the target might be quite attractive too.
>
>