Re: [myhdl-list] MEP - keep hierarchy in conversion

[David H. <da...@ad...>]

Howdy Angel --- I finished implementing a switch which ought to help with
situations where predictable output ordering would be desired.  What do you
think?

Proposed Implementation:

Every signal and generator is assigned a unique number that is incremented
after each assignment.  During just prior to output conversion, a
_convert_filter sorts siglist, memlist and genlist:

    siglist.sort(key=lambda x: x._extData['sort_order'])
    memlist.sort(key=lambda x: x.elObj._extData['sort_order'])
    genlist.sort(key=lambda x: x._extData['sort_order'])

To enable, set
    toVerilog.sorted_output = True # default is False, to match usual
semi-random output

There are no other changes required to your MyHDL design aside from
setting toVerilog.sorted_output for conversion.

It is in the repo at https://dh...@bi.../dholl/myhdl-partition
available under two branches:
The "outputsort" branch supports only the sorted_output extension.
The "partition" branch supports both partitioned_output and sorted_output
extensions, so you could simultaneously enable:
    toVerilog.partitioned_output = True
    toVerilog.separate_files = True
    toVerilog.sorted_output = True
    toVerilog(the_top, clk, rst, ...)

(Implementation Note:  This extension required no additional modifications
to MyHDL beyond those contained in my "extension_hooks" branch.  A little
monkey-patching is involved, but by keeping a small footprint for the
underlying hooks, I hope to keep pace with MyHDL's development while
maintaining the extensions for my own work.)

- David


On Thu, Oct 3, 2013 at 10:13 AM, David Holl <da...@ad...> wrote:

> On Tue, Oct 1, 2013 at 6:44 PM, Angel Ezquerra <ang...@gm...>wrote:
>
>> <snip> If multiple files were generated,
>> only some of those files would usually change, making it easier to
>> tell what changed in a given version.
>>
>> So I think that there are a few sensible reasons for wanting the
>> ability to split the generated design into files and entities.
>>
> <snip>
> Additional idea:
>
> <snip> Preserve the order of signals and generators, according to the
> order in which you originally declared them in your code ---- not the order
> that MyHDL happens to traverse your netlist.
>