Re: [myhdl-list] MEP - keep hierarchy in conversion

[Angel E. <ang...@gm...>]

On Thu, Oct 3, 2013 at 6:20 PM, Jan Decaluwe <ja...@ja...> wrote:
> On 10/02/2013 12:44 AM, Angel Ezquerra wrote:
>> I cannot comment on the ASIC side, but on the FPGA side it is a common
>> recommendation to properly organize your code into entities to improve
>> the map and/or plan and route results.
>
> I have briefly checked the Xilinx docs and I haven't found
> such a recommendation.
>

This may be one of those "folklore things" that get told from engineer
to engineer, without a proper backup. It may even have been true once,
but perhaps it is no longer the case?

I know that I've been told this by a couple of times, by different
Xilinx instructors, when I did some training classes on the Xilinx ISE
tools a few years ago. Next time we get some Xilinx guys to visit us I
will ask them if this is still the case.

Cheers,

Angel