Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/03/2013 09:25 PM, Christopher Felton wrote:

> This is how our ASICs have been developed as well, with a
> analog top-level view where the digital macros are stitched
> in with the various components.  Floorplanning is definitely
> part of the project, just not part of the HDL flow.

That is right. I am also doing such chips currently.

So I need to make a correction: when I meant "million-gate
ASICs" without floorplanning I meant the pure digital
synthesizable HDL part. (For a long time in my career, that
was basically the type of ASICs I was doing (no mixed-signal).)

Much like fully synthesizable FPGAs today, hence my
scepticism.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
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