Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

Let me do one more attempt to state clearly what I am
actually saying.

I do question the usefulness of floorplanning for FPGAs.
"Questioning" implies that I am not sure, which is why
I am asking for evidence.

This is *unrelated* to the issue of hierarchical output,
expect that I am not sure floorplanning is the best
argument.

I do *not* question the usefulness of hierarchical
converted output from MyHDL.

I have nothing against the *concept* of fine-grained
hierarchy control of the converted output.

I am convinced however that partitioning/physical/placement/
constraint control has no place in functional source
code. The technical argument is separation of concerns
as much as possible - and indeed, I think that should be
obvious to anyone with complexity management expertise.

I also think the solution should be obvious and vastly
superior - after all, you will need to write a Xilinx
or Altera partitioning configuration script *anyway*.

If you do need a nontechnical argument, it is: "Jan says no
because he finds it stupid and ugly".

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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