Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/02/2013 12:44 AM, Angel Ezquerra wrote:
> I cannot comment on the ASIC side, but on the FPGA side it is a common
> recommendation to properly organize your code into entities to improve
> the map and/or plan and route results.

I have briefly checked the Xilinx docs and I haven't found
such a recommendation.

In a document about the hierachical design flow, it is described as an
optional flow, with advantages and disadvantages.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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