Re: [myhdl-list] MEP - keep hierarchy in conversion

[Jan D. <ja...@ja...>]

On 10/02/2013 08:12 PM, David Holl wrote:

> And on the topic: in contrast to Jan's clever use of user-supplied
> code to satiate his needs of hierarchy generation, this partitioning
> code does not require the IMHO more significant changes that are
> required to pull off his hierarchy scheme.
>
> (What takes more effort?  Injecting an "@partition(...)" / "with
> partition(...):"?  Or declaring func.verilog_code = """something or
> other goes here""" with the requisite top-module convertibility?  The
> ...verilog_code="""...""" syntax is also "a significant,
> non-functional change to the source code" which also provide ample
> room for abuse by IP blocks.)

The user-defined code option likely takes more effort. And it
is indeed also a non-functional code change.

The big difference is this: it is trivial to implement it
as an optimization *add-on* while keeping the general case intact.
Just define the func.verilog_code under parameter control.
If not defined, the general case applies. And of course, you
can define it differently for different parameters.

The vision behind this is the following. Start with the
general case, e.g. a description of a specific memory
structure. If required, add an optimization for a
specific target as an *add-on*, e.g. an implementation
for xilinx, altera ... but keep the general case e.g.
for an asic.

Now you have target-independent code with target-specific
optimizations included all in the same code base.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com